Embedded and Adaptive Computing

Field Programmable Gate Arrays (FPGAs) are emerging from their traditional role as prototyping devices and are gaining popularity in commercial applications ranging from embedded control systems to power critical mobile devices. Aggressive efforts are being made to improve performance and reduce power dissipation and area to compete with custom ICs. In conjunction with technology scaling, this has resulted in high power densities and rigorous performance requirements. Previously considered second order effects have now stepped into the forefront, the most important being temperature and leakage power dissipation. Rise in on-chip temperatures and non uniform temperature gradients have numerous consequences. Temperature and leakage power have an exponential cyclic relationship, the propagation of which could lead to leakage runaway and consequently thermal failure. Secondly, excessive temperatures affect material reliability and increase the probability of electromigration induced failure. Finally, temperature rise results in performance degradation due to slower transistor switching speeds and interconnect delays. In light of the detrimental effects of temperature on future FPGA systems, it is essential to accurately profile and minimize temperatures and temperature gradients in early stages of the design flow.

Figure 1 : Framework for a thermal aware FPGA

The focus of our research is on the management of temperature distribution across FPGAs. We are developing a comprehensive framework involving innovative algorithms and architectures to create a robust system level approach to manage on-chip temperatures (Figure 1). Elevated thermal conditions are primarily due to increased power dissipation, uneven distribution of power sources and material properties. At the system level we tackle the problem by targeting the first two factors. Temperature management solutions require a light weight but accurate model of a device’s thermal activity. The model should be portable and computationally convenient. In that regard we have developed the ‘Node-Arc’ model targeted specifically for the reconfigurable FPGA fabric. It exploits uniformity in the logic element distribution in an FPGA to compute temperatures at various points in the fabric.

The response to temperature rise in a device can be static or dynamic in nature. Static techniques use a predetermined response based on estimated activity while dynamic methods intelligently modify their response based on current thermal conditions. Our methodology provides solutions on both fronts. In the static realm, we have developed a thermal aware placement tool that optimally distributes logic with an objective of reducing maximum on chip temperature and creating a more even thermal distribution (Figure 2). Our tool achieves upto 3.97 Degree Celsius reduction in maximum temperature. As power dissipation is paramount to thermal management we are also working on designing algorithms to accurately estimate FPGA power dissipation. Interconnect accounts for nearly 70% of the total power generated by an FPGA. Our models seek to estimate interconnect generated dynamic and static power. These estimates are prior to routing and are thus useful in placement tools and in the exploration of new routing architectures. The estimation framework is flexible to accommodate both static and dynamic power for a variety of routing structures. With regard to dynamic thermal management we are building intelligent systems that adapt to varying thermal conditions and actively minimize FPGA temperatures. Our solution tackles the problem at a range of granularities for an effective response with minimal performance and hardware overhead. We also exploit the flexibility of the reconfigurable fabric to tailor response mechanisms for varying activity profiles associated with different applications. Our goal is to develop a system that can observe trends in rising temperature and take proactive measures to prevent thermal failure.