Research in Embedded and Adaptive Computing group is centered around few very inter-related topics. Most of the research projects require development of ARCHITECTURES, design of ALGORITHMS, and implementation of APPLICATIONS. Our current activities are listed below. For more detailed information, please visit projects webpages for description of current and past projects.

Architecture and CAD for Field Programmable Gate Arrays

Field programmable gate arrays are user programmable devices used for rapidly implementing applications in custom hardware. As technology continues to scale down, FPGAs have also rapidly increased in density and performance.

As density increases, Placement and Routing for FPGAs need more careful attention to achieve successful design closure. Once the placement is fixed, the time spent on routing can be enormous. With increasing size and complexity of FPGA devices, CAD tools are faced with challenges related to good convergence of mapped designs in an acceptable time frame. The problems related to FPGA based design are no different from those in the custom and semi-custom ASIC arena, i.e. confidence of routability, good performance, reasonable total mapping time and more.

Prediction of wiring requirements and managing overall CAD to ensure wireability of a circuit is one problem that demands the most attention. Interconnect estimation during a design-stage is the process of predicting the routing resource requirement that the design might pose at a later stage. Interconnect prediction is gaining more and more relevance as most modern CAD tools require iterative cycles of placement and routing to converge on a solution.

This project aims at addressing interconnect estimation at various design stages. Our work in post placement interconnect prediction resulted in tools that predict interconnect requirements with almost no error. A-priori estimation techniques are a class of prediction methods that perform estimation without any knowledge of the actual placement of the circuit. These methods strictly depend on the metrics drawn from the circuit netlists. The characteristics of circuit netlist (graphs) are used to accurately predict wiring requirements. Our most currentl work addresses prediction and study of timing requirements from circuit netlists. We are modeling the timing to area tradeoff to arrive at a theory for accurate prediction of timing and wiring requirements in FPGA based designs.

Wireless Sensor Networks in Telemedicine

Wireless sensor networks (WSNs) are a rapidly growing in research and commercial development area. The potential applications for WSNs are limitless; however there are several issues to overcome in order to make them truly pervasive. One area where WSNs will be of extraordinary benefit is in the medical industry in general and in telemedicine in particular. Telemedicine involves the use of telecommunications technology to provide increased access to medical information for both patients and health care providers. The primary issues facing WSN usage in telemedicine are infrastructure installation, power generation, security concerns, device mobility and most importantly, acceptance by medical professionals.

We are currently involved in research on several issues – infrastructure installation, power generation and device mobility. Our research team is focusing on WSNs as they relate to telemedicine applications. The routers must be powered in an energy and cost efficient manner. We have developed a method to allow these nodes to be self powered. Presently, they scavenge energy from fluorescent lights (via solar panels) and use ultracapacitors for energy storage. An intelligent routing algorithm has been written to manage and utilize the scavenged energy and provide 100% on-time for the routers. Additionally, we are working to interface various medical instruments to our sensor nodes.

PAPA: Power Aware Programmable Architectures
(joint project between Prof. Bhatia and Balsara)

Reconfigurability is the NEED of the day for most system level implementations. Academic and Industrial efforts in the areas of Hardware/Software Co-design, Software Defined Radio are indicators of the future for reconfigurable computing.

The FPGAs (Field Programmable Gate Arrays) are the current day 'avatar' of Reconfigurable fabric. Devices, like FPGAs have demonstrated themselves to be strong candidates for system implementation. As semiconductor processing technology continues to evolve, the quest to put new features and functionality into such devices continues. Modern day FPGAs are complex devices supporting up to two million gates and have various mechanisms for supporting embedded cores in the form of processors and other user defined IPs.

However the scaling afforded by advances in process, is accompanied by Design challenges like Power Dissipation, Signal Integrity and Timing closure. Nonideal scaling of device parasitics, supply/threshold voltage coupled with exponential increase in leakage power now warrants new Power Aware reconfigurable architectures in UDSM(Ultra Deep Sub-Micron) regime.

This project addresses power related issues in future generations of programmable architectures. More specifically the challenges introduced by the leakage power are dealt with in more detail. We start with the FPGA architecture and explore the architectural changes needed to make it more power efficient. In order to support mechanisms for power savings effectively, the designs have to be mapped in a manner that they exploit architectural features for power saving. To enable this we also explore a unified CAD framework to exploit the power aware architecture.

We examined how temporal idleness can be effectively used to reduce leakage in a MTCMOS based Programmable Architecture. We developed a automated framework that synthesizes a Power State Controller along with a design to power off/on different temporal clusters based on their temporal activity profile. We recently completed a study on architectural component designs for power aware programmable fabrics.

Network on Chip Architectures for Future Generation Interconnections
(joint project between Prof. Bhatia and Balsara)

Network on Chip (NoC) architecture is a solution for providing on-chip communication for System-on-Chip applications. It is a packet switched network that separates communication from computation and facilitates parallel communication between the processing cores on the chip.

The transistor count on a chip has crossed billions, the number of processing elements on chip has increased to make use of this tremendous silicon resources but the on-chip communication is a major issue. The NOC overcomes the limitations of current bus-based networks by providing scalable bandwidth, parallel communication, and pipelined high speed short node to node links. It also facilitates integration and synchronization of various IP cores, error checking protocols,
and dynamic reconfiguration of the processing elements.

This network on chip is a parameterizable packet switched network. Each processing element(PE) is connected to the network through a router. The communication takes place by sending packets over the network. The network topology is modified mesh and the routers implement wormhole routing. Wormhole routing reduces the buffer space requirement on the routers and provides low latency communication. Packets are divided into flits and the
flits hop from one router node to another till it reaches the destination node. Asynchronous FIFO's provide the interface between a PE and the network.

This packet switched on-chip network has been modelled using RTL for validating the architecture. The network was synthesized for Xilinx virtex-II FPGAs. The routers operate at 200MHz and occupy 5% (each) of the slices available on Xilinx(V2P1000) FPGA. The best case aggregate bandwidth for a 6-node network is above 1GBps. The average case bandwidth depends on the communication pattern between the nodes and the mapping of the application to the network nodes.

Currently, we are looking into implementing system level applications on this network to evaluate the network performance and also dynamic reconfigurable applications on this communication network.

Jaunt

There are topics in system level design that are very interesting and relatively unexplored. These projects are initial investigations in these areas where we are interested in integration of sensors, biometrics, reconfigurable computing, and systems software to define pervasive computing environments.


 
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